Ultra Low Power DSP for Health Care Monitoring
Wireless medical technologies have created opportunities for new methods of preventive care using biomedical implanted and body-worn devices. The design of the technologies that will enable these applications requires correct delivery of the vital physiological signs of the patient along with the energy management in power-constrained devices. The high cost and even higher risk of battery replacement require that these devices be designed and developed for minimum energy consumption.
In this research, we explore a variety of ultra low-power DSP techniques for wearable biomedical devices. A blend of feature engineering and machine learning algorithms are employed and evaluated within the context of real-time classification applications. The evaluation is based on two major criteria: 1. classification accuracy and 2. algorithmic complexity (computation, memory, latency). Currently, two case studies are being explored. The first case study is the detection of seizures for epileptic patients using multi-physiological signals in an ambulatory setting. The second case study is an assistive technology that enables a user to interactive with their surroundings using a tongue-driven interface.
Deep Neural Nets for Embedded Big Data Applications
We explore the use of deep neural networks (DNN) for embedded big data applications. Deep neural networks have been demonstrated to outperform state-of-the-art solutions for a variety of complex classification tasks, such as image recognition. The ability to train networks to both perform feature abstraction and classification provides a number of key benefits. One key benefit is that it reduces the burden of the developer to produce efficient, optimal feature engineering, which typically requires expert domain-knowledge and significant time. A second key benefit is that the network's complexity can be adjusted to achieve desired accuracy performance. Despite these benefits, DNNs have yet to be fully realized in an embedded setting. In this research, we explore novel architecture optimizations and develop optimal static mappings for neural networks onto highly parallel, highly granular hardware processors such as many-cores and embedded GPUs.
LESS: Light Encryption using Scalable Sketching
LESS framework is adopted to accelerate Big Data processing on Hardware Platforms. LESS can achieve reduction in data communications up to 67%, while achieving 3.81dB Signal to Reconstruction Error Rate. LESS framework has been applied to Face Detection, Objects and Scenes identification, Text analysis and Bio-medical applications. Integration of LESS framework with Hadoop MapReduce Platform shows that, it achieves 46% reduction in data transfers with very low execution overhead of 0.11% and negligible energy overhead of 0.001% when tested for 50,000 number of image.
Energy Efficient Secured Many-Core Processor for Embedded Applications
The goal of this research is to design a real-time Trojan detection framework for a custom Many-Core by using an effective method such that it has minimal hardware overhead and implementation complexity with a very high accuracy of detection.
Efficient Compressive Sensing Reconstruction Algorithms and Architectures
Compressive sensing (CS) is a novel technology which allows sampling sparse signals under sub-Nyquist rate and reconstructing the image using computational intensive algorithms. Reconstruction algorithms are complex and software implementation of these algorithms is extremely slow and power consuming. In this project, we are proposing reduced complexity reconstruction algorithms and efficient hardware implementation on different platforms including FPGA, ASIC, GPU, and many-core platforms.