Implementing Low Power Error Correction Hardware for Next Generation Communication Applications

Abstract:

Many emerging and future communication applications
require a significant amount of high throughput data
processing and operate with decreasing power budgets. This
need for greater energy ececiency and improved performance
of electronic devices demands a joint optimization of algorithms,
architectures, and implementations.
Low Density Parity Check (LDPC) decoding has received
significant attention due to its superior error correction performance,
and has been adopted by several recent communication
standards. Due to the codes’ inherently irregular and global
communication patterns, high-speed systems that require many from large wire dominated
circuits with low clock rates. The recently introduced Split-
Row Threshold decoding algorithms and architectures increase
parallelism, and significantly reduce wire interconnect complexity.
Several Multi-Split-Row Threshold decoders have been
implemented in 65 nm CMOS for a (2048,1723) LDPC code
compliant with the 10GBASE-T Ethernet standard. The impact
of different levels of partitioning on error performance, wirennect complexity, decoder area, power dissipation and
speed are investigated. A 16-way Split-Row Threshold decoder
occupies 4.8 mm2, operates at 195 MHz at 1.3 V with an average
throughput of 92.8 Gbps with early-termination enabled. The
decoder achieves improvements in area, throughput and energy
ececiency of 4.1, 3.3, and 4.8 respectively, compared to a
conventional implementation.

Paper

• PDF (154 KB),   (c) Copyright, 2011, IEEE

Presentation

• PPT (3.3 MB),   (c) Copyright, 2011

Reference

T. Mohsenin, "Implementing Low Power Error Correction Hardware for Next Generation Communication Applications" In Proceedings of the Grace Hopper Celebration of Women in Computing 2011 New Investigators Technical Papers (GHC'11), May 2011, pp..

BibTeX Entry

@INPROCEEDINGS{Mohsenin:GHC,
    author={Mohsenin, T.},
    booktitle={Grace Hopper Celebration of Women in Computing 2011 New Investigators Technical Papers}, 
    title={Implementing Low Power Error Correction Hardware for Next Generation Communication Applications},
    year={2011},
    month={November},
    pages={},
    doi={}
}