High Performance Compressive Sensing Reconstruction Hardware with QRD Process

Abstract:

This paper presents a high performance architecture for the reconstruction of compressive sampled
signals using Orthogonal Matching Pursuit (OMP) algorithm. Q-R decomposition (QRD) process is used for 
the matrix inverse core and a new algorithm for finding fast inverse square root of a fixed point number 
is also implemented to support the QRD process. The optimized architecture takes 256-length input vector 
and 64 measurement data, and reconstructs a signal of sparsity 8. The design is implemented in 65 nm CMOS 
which runs at 165 MHz and occupies 0.69 mm^2, total reconstruction takes 13.7 us. The implementation on 
Xilinx FPGA Virtex-5 takes 27.12 us to reconstruct a 256--length signal of sparsity 8. The same 
architecture for 128--length signal of sparsity 5 on Virtex--5 is 2.4 times faster than the 
state--of--the--art implementation.

Paper

• PDF (1.07 MB),   (c) Copyright, 2012, IEEE

BibTeX Entry

@INPROCEEDINGS{CSOMP:ISCAS,
    author={Stanislaus, J.L.V.M. and Mohsenin, T.},
    booktitle={Circuits And Systems, 2012. ISCAS 2012. IEEE International Conference on}, 
    title=High Performance Compressive Sensing Reconstruction 
		Hardware with QRD Process},
    year={2012},
    month={May.},
    pages={},
    doi={}
}